An integrated circuit (IC) layout specifies portions of various components of an IC. When the IC is to include a large number of registers, latches, flip-flops, and/or other types of clocked devices (“sinks”) that are to be clocked by one or more clocks, the IC must include one or more clock trees for delivering the clock signal from the clock source to all of the sinks to be clocked by it. A clock tree distributes a clock signal from its root to a set of sinks within an IC through a branching network of drivers (e.g., buffers or inverters). A single driver distributes the clock signal to a grouping of other drivers and/or sinks Connectivity between a driver and its fanout is represented by a “clock net” and will be physically implemented by routed wires.
Electronic design automation (EDA) software systems commonly perform clock-tree synthesis (CTS). Conventional approaches to CTS typically include a global wirelength reduction stage and a detailed wirelength reduction stage. During the global wirelength reduction stage, components of the clock tree (referred to hereinafter as “clock tree instances”) are interconnected using a Steiner-tree approach in which the components are aligned to a Steiner route between their parents and children. During the detailed wirelength reduction stage, a compass-search algorithm is used to iteratively move clock tree instances to different locations, and a validation is performed at each move to verify that the move results in a reduction in wirelength and conforms with design constraints (e.g., skew and slew). However, the compass-search algorithm-based wirelength reduction is slow because it uses a brute-force approach that tests locations in an unguided way. While it does use the results it has found to guide future searches, storing and maintaining this information utilizes a large amount of computational resources. Additionally, to save runtime, the compass-search algorithm is “greedy,” so the algorithm can easily get stuck in a local minimum, which means that despite the high runtime, the algorithm may not find an optimal location.